1. Field of the Invention
The present invention relates to a touch panel sensing circuit.
2. Description of the Prior Art
A conventional panel determines the touch points according to capacitance variances on said touch panel. Please refer to FIG. 1, which illustrates a conventional touch panel sensing circuit 100. As shown in FIG. 1, the touch panel sensing circuit 100 includes a sensing device 110, a capacitance sensing circuit 120, an analog-to-digital converter 130, and a digital signal processing unit 140. The sensing device 110 includes a sensing capacitor Csense. While a user touches the touch panel, for example, by pressing, so as to trigger a corresponding touch command, capacitance of the sensing capacitor Csense is raised; at this time, the sensing device 110 transmits the raised capacitance of the sensing capacitor Csense to the capacitance sensing circuit 120, which transforms the raised capacitance into a corresponding analog voltage; the analog-to-digital converter 130 transforms the analog voltage into a corresponding digital signal; and at last, the digital signal processing unit 140 performs digital processing on the digital signal so as to determine the touch command triggered by the user. The capacitance sensing circuit 120 includes an equivalent capacitor Cin, which is actually connected with the sensing capacitor Csense in parallel. While the touch panel having the touch panel sensing circuit 100 shown in FIG. 1 acquires a larger area, the capacitance of the equivalent capacitor Cin is raised as well, so that a capacitance variance of the sensing capacitor Csense caused by the user is getting less obvious, and the complexity of sensing the command triggered by the user for large-area touch panels is raised as a result.
Please refer to FIG. 2 and FIG. 3. FIG. 2 illustrates the capacitance sensing circuit 120 shown in FIG. 1. FIG. 3 illustrates voltage levels at certain nodes within the capacitance sensing circuit 120 shown in FIG. 2. As shown in FIG. 2, the capacitance sensing circuit 120 includes a plurality of transistors T1, T2, T3, T4, a plurality of comparators OPref, OPCOM, an equivalent capacitor Cin, and a D flip-flop DFF. As shown in FIG. 2, the transistors T1 and T2 form a current mirror, where a width-to-length ratio, i.e., W/L, is assumed to be K1:1, and K1 indicates a positive integer. An amplitude of a current IT1 flowing through the transistor T1 is proportional to a capacitance of the sensing capacitor Csense. In the capacitance sensing circuit 120, the current IT1 is used for charging the equivalent capacitor Cin, and a voltage level of a voltage Vramp at the drain of the transistor T2 is raised from zero gradually. A raising time of the voltage Vramp from zero to a voltage VH is counted by accumulating clocks, such as the analog-to-digital counting shown in FIG. 3; at last, the count of the raising time is processed by the digital signal processing unit 140 so as to retrieve the capacitance of the sensing capacitor in a form of digital signal, i.e., the output signal OUTPUT shown in FIG. 1, where a magnitude of the current IT1 is proportional to the capacitance of the sensing capacitor Csense. Because of the amplification brought by the current mirror, the magnitude of the current IT1 equals K1 times of a magnitude of the current IT2, which flows through the transistor T2, and the following equations may be inducted thereby:
                                          IT            ⁢                                                  ⁢            2                    =                                                    1                                  K                  ⁢                                                                          ⁢                  1                                            ⁢              IT              ⁢                                                          ⁢              1                        =                                          K                ′                            ⁢              Csense                                      ;                            (        1        )                                                      IT            ⁢                                                  ⁢                          2              ·                              t                up                                              =                                    C              in                        ·                          V              H                                      ;                            (        2        )                                                      t            up                    =                                                                      C                  in                                ·                                  V                  H                                                            IT                ⁢                                                                  ⁢                2                                      =                                                                                C                    in                                    ·                                      V                    H                                                                                        K                    ′                                    ⁢                  Csense                                            =                              K                ⁢                                                      C                    in                                                        C                    sense                                                                                      ;                            (        3        )            
Note that tup indicates the raising time of the voltage level of the voltage Vramp from zero to the voltage VH gradually. K and K′ are parameters. The equation (1) indicates a proportional relation between the currents IT1, IT2 and the capacitance of the sensing capacitor Csense. The equation (2) indicates a condition that a total charge stored on the capacitor Cin by the current IT2 equals the capacitance of the equivalent capacitor Cin multiplied by the voltage VH, and as a matter of fact, equals to the equivalent capacitor Cin multiplied by a voltage difference between the voltage VH and a ground voltage VSS, which is assumed to acquire zero voltage level. The equation (3) may be inducted according to the equations (1) and (2). As can be observed from the equation (3), the capacitance of the equivalent capacitor Cin is proportional to the raising time tup; in other words, the capacitance of the equivalent capacitor Cin can be calculated according to the raising time tup. Besides, while the capacitance of the equivalent capacitor Cin is getting larger, a longer raising time tup is introduced as a result, and a higher resolution of the digital signal OUTPUT may be retrieved with the aid of the longer raising time tup. However, since a larger capacitance of the equivalent capacitor Cin requires a larger area and/or volume of a touch panel, producing the touch panel with a larger area and/or volume for retrieving a higher capacitance of the equivalent capacitor Cin may not be an efficient way.